module tb;

logic clk;
logic rstn;

logic x3 ;
logic x26;
logic x27;

always_comb begin
	x3 = tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[3];
	x26 = tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[26];
	x27 = tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[27];
end

initial begin : clk_gen
	clk = 1'b1;
	forever begin
		#10;
		clk = ~clk;
	end
end

initial begin : rstn_gen
	rstn <= 1'b0;
	#30;
	rstn <= 1'b1;	
end

//rom 初始值
initial begin
	$readmemh("../../sim/inst_data.txt",tb.u_LilyRiscv_top.u_rom.rom_mem);
end

integer r;
initial begin
	wait(x26 == 32'b1);
	
	#200;
	if(x27 == 32'b1) begin
		$display("############################");
		$display("########  pass  !!!#########");
		$display("############################");
	end
	else begin
		$display("############################");
		$display("########  fail  !!!#########");
		$display("############################");
		$display("    fail testnum = %2d", x3);
		for(r = 0; r < 32; r ++)begin
			$display("x%2d register value is %d", r, tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[r]);	
		end	
	end
	$finish(); // 注意，必须主动结束
end

LilyRiscv_top u_LilyRiscv_top(
	.clk   		(clk),
	.rstn 		(rstn)
);
	
endmodule : tb